1. Field of the Invention
A communication apparatus according to the present invention relates particularly to a communication apparatus that judges which clock of which phase, among multiphase clocks, should be selected.
2. Description of the Related Art
When data is transmitted and received between different semiconductor apparatuses, delay or jitter of a signal occurs on the transmission line. In this case, if the semiconductor apparatuses which perform transmission and receiving of the data operate on the basis of clock signals which are in an asynchronous relationship with each other, there is a problem that the data is not correctly received by the receiving-side apparatus. Accordingly, the receiving-side apparatus controls the phase of a clock used in receiving the data to correctly perform data receiving. An example of a method for the receiving-side apparatus to control the phase of the clock used in data receiving as described above is disclosed in Japanese Patent Laid-Open No. 8-8811.
FIG. 6 shows a block diagram of a synchronization pull-in apparatus 100 described in Japanese Patent Laid-Open No. 8-8811. The synchronization pull-in apparatus 100 shown in FIG. 6 has a unique word (UW) detector 102, a TDMA timing generator 107, a phase detector 106, a microprocessor 120, a correction counter 124, a 1/n frequency divider 103, a corrector 104 and a 1/m frequency divider 105.
The unique word detector 102 detects a unique word from serial digital received data which is obtained by demodulating a radio wave from a base station by a demodulator 101 and a receiving clock, and outputs the detection timing. The TDMA timing generator 107 generates a TDMA timing at a symbol clock and generates a transmission slot timing and receiving slot timing of the synchronization pull-in apparatus 100. The phase detector 106 compares the phases of the symbol timing at the time of receiving and the symbol clock of the synchronization pull-in apparatus 100 according to the unique word detection timing, and outputs the value of the phase difference. The microprocessor 120 calculates the correction amount of the basic clock on the basis of the phase difference value outputted by the phase detector 106 and instructs correction of advance/delay. The correction counter 124 generates a correction timing on the basis of the correction amount specified by the microprocessor 120. The 1/n frequency divider 103 reduces a clock corresponding to (n×m) times the symbol timing frequency at the time of receiving to 1/n to generate the basic clock. By performing clock deletion for the basic clock in the case where the correction timing outputted by the correction counter 124 is for advance correction and performing clock insertion for the basis clock in the case of delay correction, the corrector 104 outputs a synchronization-corrected clock obtained by performing the correction operation. The 1/m frequency divider 105 reduces the synchronization-corrected clock to 1/m to output a symbol clock indicating the symbol timing of the synchronization pull-in apparatus 100.
In the synchronization pull-in apparatus 100, the microprocessor 120 calculates the correction amount of the basic clock on the basis of the value of the phase difference between the symbol timing at the time of receiving, which has been detected by the phase detector 106, and the phase of the symbol clock of the synchronization pull-in apparatus 100. Then, by operating on the basis of the basic clock corrected with the calculated correction amount, the synchronization pull-in apparatus 100 secures operation compatibility with the base station.
However, in the synchronization pull-in apparatus 100, since the correction amount is calculated by the microprocessor 120, it takes much time to perform the arithmetic operation. Therefore, there is a problem that the basic clock correction timing is later than the receiving timing. There is a problem that, when such delay occurs, it is not possible to correctly process the data of the beginning part of received data. Recently, the data transmission speed has been improved, and the influence of the correction timing delay upon data processing is becoming a more noticeable problem.